The ATMega 328 processor has multiple 10 bit ADC (Analog to Digital Converter) ports. By default it takes 111 microseconds to read an analog value, thus the default sampling frequency is 9KHz. But it is possible to configure the chip to read at 62.5 KHz with little loss of resolution, then the reading delay will be of 16 us.
You can use the following code to do that:
#ifndef cbi
#define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit))
#endif
#ifndef sbi
#define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit))
#endif
void setup() {
sbi(ADCSRA,ADPS2) ;
cbi(ADCSRA,ADPS1) ;
cbi(ADCSRA,ADPS0) ;
}
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